The present invention relates generally to a magnetic memory cell with a soft ferromagnetic reference layer having a non-pinned orientation of magnetization. More specifically, the present invention relates to a magnetic memory cell with a soft ferromagnetic reference layer having a non-pinned orientation of magnetization and including a read conductor that is completely surrounded by a ferromagnetic cladding so that a read magnetic field generated by a current flowing in the read conductor does not saturate and is substantially contained within the ferromagnetic cladding and the orientation of magnetization of the soft ferromagnetic reference layer is dynamically pinned-on-the-fly to a desired orientation by the read magnetic field.
A magnetic memory such as a magnetic random access memory (MRAM) is a non-volatile type of memory that is being considered as an alternative data storage device in applications where traditional data storage devices such as DRAM, SRAM, Flash, and hard disk drives have been used. An MRAM typically includes an array of magnetic memory cells. For instance, a prior magnetic memory cell can be a tunneling magnetoresistance memory cell (TMR), a giant magnetoresistance memory cell (GMR), or a colossal magnetoresistance memory cell (CMR) that includes a data layer (also called a storage layer or bit layer), a reference layer, and an intermediate layer between the data layer and the reference layer. The data layer, the reference layer, and the intermediate layer can be made from one or more layers of material. The data layer is usually a layer or a film of magnetic material that stores a bit of data as an orientation of magnetization that may be altered in response to the application of external magnetic fields. Accordingly, the orientation of magnetization of the data layer (i.e. its logic state) can be rotated (i.e. switched) from a first orientation of magnetization that can represent a logic xe2x80x9c0xe2x80x9d, to a second orientation of magnetization that can represent a logic xe2x80x9c1xe2x80x9d, or vice-versa. On the other hand, the reference layer is usually a layer of magnetic material in which an orientation of magnetization is xe2x80x9cpinnedxe2x80x9d(i.e. fixed) in a predetermined direction. The predetermined direction is determined by microelectronic processing steps that are used to fabricate the magnetic memory cell.
Typically, the logic state (i.e. a xe2x80x9c0xe2x80x9d or a xe2x80x9c1xe2x80x9d) of a magnetic memory cell depends on the relative orientations of magnetization in the data layer and the reference layer. For example, in a tunneling magnetoresistance memory cell (a tunnel junction memory cell), when an electrical potential bias is applied across the data layer and the reference layer, electrons migrate between the data layer and the reference layer through the intermediate layer (a thin dielectric layer usually called a tunnel barrier layer). The phenomenon that causes the migration of electrons through the barrier layer may be referred to as quantum mechanical tunneling or spin tunneling. The logic state can be determined by measuring the resistance of the memory cell. For example, the magnetic memory cell is in a state of low resistance if the overall orientation of magnetization in its data storage layer is parallel to the pinned orientation of magnetization of the reference layer. Conversely, the tunneling junction memory cell is in a state of high resistance if the overall orientation of magnetization in its data storage layer is anti-parallel to the pinned orientation of magnetization of the reference layer. As was mentioned above, the logic state of a bit stored in a magnetic memory cell is written by applying external magnetic fields that alter the overall orientation of magnetization of the data layer. Those external magnetic fields may be referred to as switching fields that switch the magnetic memory cell between its high and low resistance states.
FIG. 1 illustrates a prior tunnel junction memory cell 100 that includes a data layer 110, a reference layer 112, and an insulating barrier layer 114 that is positioned between the data layer 110 and the reference layer 112. Additionally, the memory cell 100 can include a first electrically conductive node 116 connected with the data layer 110 and a second electrically conductive node 118 connected with the reference layer 112. An externally supplied current can be passed through the first and second electrically conductive nodes (116,118) to generate the aforementioned external magnetic fields. The first and second electrically conductive nodes (116, 118) can be the row and column conductors in a memory array that includes a plurality of the memory cells 100 as will be discussed in reference to FIGS. 4a and 4b below. The nodes can also be used to measure the resistance of the memory cell 100 so that its logic state can be determined. The reference layer 112 has an orientation of magnetization M1 that is pinned in a predetermined direction as illustrated by a left-pointing arrow. The data layer 110 has an alterable orientation of magnetization M2 as illustrated by the double arrow.
In FIG. 2a, the orientation of magnetization M2 of the data layer 110 is parallel (i.e. the arrows point in the same direction) to the orientation of magnetization M1 of the reference layer 112, resulting in the memory cell 100 being in a low resistance state. On the other hand, in FIG. 2b, the orientation of magnetization M2 of the data layer 110 is anti-parallel (i.e. the arrows point in opposite directions) to the orientation of magnetization M1 of the reference layer 112, resulting in the memory cell 100 being in a high resistance state.
Because the data layer 110 and the reference layer 112 are made from ferromagnetic materials that are positioned in close proximity to each other, the pinned orientation of magnetization M1 of the reference layer 112 generates a demagnetization field D that extends from an edge domain of the reference layer 112 to the data layer 110 as illustrated in FIG. 2c. FIG. 2d illustrates the effect of the demagnetization field D on the orientation of magnetization M2 of the data layer 110. Ideally, the orientation of magnetization of the data layer 110 would have an alignment that is either parallel or anti-parallel to the pinned orientation of magnetization M1. However, because of the demagnetization field D, there is a small angular displacement xcex8 between an ideal orientation of magnetization M2xe2x80x2 (shown as a dashed arrow) and an actual orientation of magnetization M2 (shown by a solid arrow). The angular displacement xcex8 results in a reduction in a magnitude of change in magnetoresistance xcex94R/R between the high and low states (i.e. parallel or anti-parallel). It is desirable to have the magnitude of change in magnetoresistance xcex94R/R be as large as possible so that it is easier to detect the state of the bit in the data layer 110. Essentially, xcex94R/R is like a signal-to-noise ratio S/N. During a read operation, a higher SIN results in a stronger signal that can be sensed to determine the state of the bit in the data layer 110. Therefore, one disadvantage of the prior tunnel junction memory cell 100 is the reduction in the magnitude of change in magnetoresistance xcex94R/R (i.e. a lower SIN during a read operation) resulting from the angular displacement xcex8.
Another disadvantage of the prior tunnel junction memory cell 100 is that pinning the orientation of magnetization M1 of the reference layer 112 often requires more than one layer of material to effectuate the pinning. For instance, in FIG. 3a, a prior tunnel junction memory cell 200 includes the aforementioned data layer 210, first and second electrically conductive nodes (216, 218), and also includes a composite reference layer 212, 212a, and 212b that is a sandwich of different materials. The layer 212 is referred to as an antiferromagnet layer (a pinning layer) and the layer 212a is a pinned reference layer. The pinning layer 212 magnetize the orientation of magnetization M1 of the reference layer 212a in a desired direction. The layer 212b is a seed layer. Examples of materials used for the pinning layer 212, the reference layer 212a, and the seed layer 212b include: FeMn, IrMn, NiMn, or PtMn for the pinning layer 212; NiFe, NiFeCo, or CoFe for the reference layer 212a; and NiFe, or NiFeCo for the seed layer 212b. 
Alternatively, a prior tunnel junction memory cell 300 having a pinning layer 312 of greater complexity than that shown in FIG. 3a is illustrated in FIG. 3b. The prior tunnel junction memory cell 300 includes the aforementioned data layer 310, first and second electrically conductive nodes (316, 318), and also includes a composite reference layer 312, 312a, 312b, and 312c, that is a complex sandwich of different materials. The pinning layer 312 sets the magnetization orientation of an artificial antiferromagnet 312c that has an even more complicated structure than the antiferromagnet layer 212 of FIG. 3a. The artificial antiferromagnet 312c can be a sandwich of materials such as: Co/Ru/Co; or CoFe/Ru/ CoFe, for example. In FIG. 3b, layer 312a is the pinned reference layer, layer 312b is the seed layer, and layer 312 is the antiferromagnet layer (pinning layer).
Therefore, one disadvantage of the prior tunnel junction memory is that it requires more layers in its structure to form the reference layer. Because of the extra materials required to form those layers, extra microelectronic processing steps are required to fabricate the prior tunnel junction memory cells 200 and 300. Those extra steps can result in the possibility of defects being introduced into the tunnel junction memory that can cause the memory to be defective as manufactured or to later fail in a product that incorporates the memory. It is desirable to minimize the complexity and therefore the number of processing steps required to fabricate the memory in order to reduce defects and increase yield. Furthermore, the materials necessary to form the reference layer are themselves difficult materials to manufacture. For mass production of magnetic memories, it is desirable to use materials that are easy to make so that the manufacturing process is simplified and manufacturing costs are reduced.
An additional disadvantage of the prior tunnel junction memory is that the reference layer must be heated at an elevated temperature in an annealing step. Annealing takes time (an hour or more) and requires the magnetic memory to be subjected to temperatures ranging from200 to 300 degrees centigrade under a constant magnetic field. Because setting the orientation of magnetization requires annealing in a magnetic field, there is a possibility that if the magnetic memory is later subjected to high temperatures, the pinning of the reference layer may become xe2x80x9cunsetxe2x80x9d and lose its orientation of magnetization. To reset the orientation of magnetization, another annealing step would be required.
Another disadvantage of the prior tunnel junction memory cell 100 is illustrated in FIGS. 4a and 4b. In FIG. 4a, a magnetic memory 150 includes a plurality of the memory cells 100 configured in a cross point array. The first electrically conductive node 116 is replicated to form row conductors (Row1 and Row2) that cross the memory cells 100 and the second electrically conductive node 118 is replicated to form column conductors (Col1, Col2, and Col3) that also cross the memory cells 100 (i.e. a memory cell 100 is located at the intersection of a row and column conductor). A memory cell 100a located at the intersection of Row2 and Col3 is selected for a read operation by connecting a voltage source V to Row2 with Row1 left floating. Col1 and Col2 are connected to GND and Col3 is connected to a sense amp S which is connected to a virtual ground. Consequently, a current path is formed and a current I flows into conductive node 116 of Row2. A portion of the current I flows to GND as indicated by currents IG. However, another portion of the current I comprises a read current IR that is sensed by the sense amp S. The magnitude of IR is indicative of the orientation of magnetization of the bit of data stored in the memory cell 100a, but the magnitude of IR is not sufficient to rotate the orientation of magnetization of the data layer during the read operation.
In FIG. 4b, the selected memory cell 100a is shown in greater detail. The current IR generates a magnetic field HR in accordance with the right-hand rule. The disadvantage arises from the magnetic field HR extending radially outward from its respective conductors (i.e. fringe fields) and interacting with adjacent memory cells 100 in the array. Depending on the proximity of the memory cells 100 to each other and on the magnitude of the current IR, those fringe fields can corrupt a data bit stored in the data layer 100 of neighboring memory cells 100 that have not been selected for a read operation.
Moreover, another disadvantage of the prior tunnel junction memory cell 100 is that the magnitude of the current IR necessary to read data from a selected memory cell 100 can be quite large. Although not shown in FIGS. 4a and 4b, the magnitude of write currents necessary to flip the orientation of magnetization of the data layer 100 can also be quite large and are typically greater in magnitude than the current IR. The current IR can result in the generation of unwanted waste heat that can require thermal management systems such as cooling fans or the like to remove the waste heat. Thermal management systems can add to the cost, size, weight, and noise of an electronic system that incorporates the memory 150. For portable electronic systems that rely on a battery as a source for power or for electronic systems that are designed to be energy efficient, the aforementioned currents can increase power consumption thereby reducing battery life or can increase power drain thereby undermining energy efficiency.
Although the above disadvantages have focused on a tunnel junction memory cell (i.e. a TMR memory cell), those disadvantages also apply to other types of magnetic memory cells such as the aforementioned GMR and CMR memory cells. For instance, as is well understood in the art, for a GMR memory array (not shown) the cross point array is replaced with gate transistors (i.e. FET""s) that electrically isolate the GMR memory cells. The FET""s are electronically switched on or off to select a specific GMR cell for a read operation. A read current flowing through the selected memory cell can be sensed by a sense amp or the like.
Therefore, there is a need for a magnetic memory cell having a reference layer that does not require a pinned orientation of magnetization in order to read a bit of data stored in the data layer. There is also a need to reduce the number of layers of material that are required to form the reference layer. Moreover, there exists a need for a magnetic memory cell in which fringe fields generated during a read operation are substantially confined to the reference layer so that interference with nearby memory cells is substantially reduced. Finally, there is a need for a magnetic memory cell in which angular displacement of the orientation of magnetization of the data layer is substantially reduced or eliminated so that there is a high magnitude of change in magnetoresistance during a read operation.
The present invention is an improvement in the design of magnetic memory cells such as tunneling magnetoresistance memory cells (TMR), giant magnetoresistance memory cells (GMR), and memories incorporating those types of magnetic memory cells. Moreover, the present invention includes improvements in the materials used for the reference layer of a magnetic memory cell and the structure used for the read conductor of a magnetic memory cell.
Broadly, the present invention is embodied in a magnetic memory cell including a ferromagnetic data layer for storing a bit of data as an alterable orientation of magnetization, an intermediate layer connected with the ferromagnetic data layer, and a soft ferromagnetic reference layer connected with the intermediate layer and including a read conductor and a ferromagnetic cladding that completely surrounds the read conductor to form a cladded read conductor. The soft ferromagnetic reference layer has a non-pinned orientation of magnetization (i.e. the orientation of magnetization is not set in a predetermined direction). When an externally supplied current flows through the read conductor, the read conductor generates a magnetic field. The ferromagnetic cladding is not saturated by the magnetic field and substantially contains the magnetic field within the ferromagnetic cladding. During a read operation, the externally supplied current is passed through the read conductor so that an orientation of magnetization of the soft ferromagnetic reference layer is pinned-on-the-fly to a desired direction and the bit of data stored in the data layer is read by measuring a resistance between the data layer and the soft ferromagnetic reference layer.
An added benefit of the cladded read conductor of the present invention is that fringe fields are significantly reduced because the magnetic field from the read conductor is contained substantially within the ferromagnetic cladding.
During a read operation, the ferromagnetic cladding of the present invention provides a closed flux path (flux closure) for the read magnetic field. As a result, the demagnetization filed of prior magnetic memory cells is substantially reduced or eliminated so that angular displacement is minimized and there is a higher magnitude of change in magnetoresistance during a read operation.
The disadvantages of the prior pinned reference layer are solved by the soft ferromagnetic reference layer of the present invention because a read operation does not require that the orientation of magnetization of the soft ferromagnetic reference layer be pinned. Instead, to effectuate a read operation, the orientation of magnetization of the soft ferromagnetic reference layer of the present invention is dynamically pinned (i.e. pinned-on-the-fly) to a desired direction by passing a current of predetermined magnitude and direction through the read conductor. Consequently, the aforementioned additional layers of material, the complexity of those layers of material, and the microelectronics processing steps necessary to form those layers are reduced. The need to anneal the reference layer in a magnetic field is eliminated by the soft ferromagnetic reference layer of the present invention. Moreover, the possibility of having to xe2x80x9cresetxe2x80x9d the orientation of magnetization of the reference layer if the memory is subjected to heat is mooted by the soft ferromagnetic reference layer of the present invention because the orientation of magnetization is pinned-on-the-fly.
Another advantage of the magnetic memory cell of the present invention is that the magnitude of a read current necessary to effectuate a read operation is reduced so that power dissipation (waste heat) and power consumption are reduced. The current for the read or the write operation can be a static dc current or it can be a dynamic current pulse. As was mentioned previously, it is desirable to minimize power consumption and waste heat generation, particularly in portable battery operated systems and energy efficient systems.
During a read operation, the ferromagnetic cladding of the present invention provides a closed flux path (flux closure) for the read magnetic field. As a result, the demagnetization filed of prior magnetic memory cells is substantially reduced or eliminated so that angular displacement is minimized and there is a higher magnitude of change in magnetoresistance during a read operation.
In one embodiment of the present invention, the magnetic memory cell includes a ferromagnetic cap layer that is positioned between the ferromagnetic cladding and the intermediate layer and is magnetically coupled with the ferromagnetic cladding. During a read operation, the magnetic field does not saturate and is substantially contained within the ferromagnetic cladding and the ferromagnetic cap layer.
In another embodiment of the present invention, the data layer, the ferromagnetic cap layer and the ferromagnetic cladding can be made from a high magnetic permeability soft magnetic material. In another embodiment of the present invention, the data layer, the ferromagnetic cap layer, and the ferromagnetic cladding are made from an identical high magnetic permeability soft magnetic material.
In yet another embodiment of the present invention, the data layer, the ferromagnetic cap layer, and the ferromagnetic cladding can be made from a low coercivity material.
In one embodiment of the present invention, the data layer is in electrical communication with a first conductor that crosses the data layer. During a read operation, the bit is read by measuring a resistance between the soft ferromagnetic reference layer and the first conductor.
In another embodiment of the present invention, a second conductor crosses the data layer and the first and second conductors generate first and second write magnetic fields respectively in response to externally supplied currents. The first and second write magnetic fields cooperatively interact with the data layer to rotate the alterable orientation of magnetization of the data layer to a desired direction thereby writing a new bit of data to the ferromagnetic data layer.
In alternative embodiments of the present invention, the magnetic memory cell can be a tunneling magnetoresistance memory cell and a giant magnetoresistance memory cell.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.